1. Field of the Invention
This invention relates to a radio signal receiver, and particularly to estimation of and removal of direct current (DC) components in received complex base band (CBB) signals.
2. Description of the Related Art
Radio frequency (RF) signal receivers generally share a basic structure 10 as shown in FIG. 1. A signal received by antenna 12 is filtered (14) to separate a signal at a particular desired frequency, normally referred to as a channel, from other components of the received signal. Most RF receivers would also include a gain stage 16, followed by further receiver processing block 18, the nature of which will depend on the particular receiver and its application. Such functions as demodulation, decoding and further signal processing would be included in block 18. Various control signals for the filter and gain stages can be generated by processing block 18 and supplied as inputs to these stages over control signal paths 22.
The receiver 10 is a very general receiver structure and is intended only as an illustration thereof. The implementation of this general structure will vary considerably, depending upon the particular receiver application and manufacturer. For example, different receivers may obviously operate in different frequency bands and detect different channels, leading to differences in filter design. The gain stages of different receivers will also vary, depending for example upon required receiver dynamic range, which will be dependent upon the intended application of the receiver. Different manufacturers may also use different components to realize the various receiver circuits.
FIG. 2 shows a more detailed block diagram of a known radio receiver 20. The receiver 20 includes two filter stages 14a and 14b, roughly corresponding to filter stage 14 of receiver 10. Filters 14a and 14b are both band pass filters, although the bandwidth of channel filter 14b is narrower than that of frequency band filter 14a. Between the filter stages 14a and 14b, receiver 20 includes a low noise amplifier (LNA) and frequency down conversion stage 24 for amplifying the filtered signal from the filter 14a and converting from RF to intermediate frequency (IF). As in receiver 10, receiver 20 includes a gain stage 16, controlled by a gain control signal that is generated by the receiver processing block 18.
The addition of quadrature mixer 26 into the general receiver structure will be obvious to those skilled in the art to which the instant invention pertains. Quadrature mixture 26 separates the in-phase (I) and quadrature (Q) components of the CBB received signal, as shown at the output of mixer 26. Low pass filters 28a and 28b filter out image signal components, from the mixer 26 output, and limit the input bandwidth sampled by the analog to digital converters (ADCs) 32a and 32b. The ADCs 32a and 32b are also included in receiver 20, since most modem receivers perform signal processing functions in the digital domain.
Digital outputs from the ADCs 32a and 32b are input to a digital signal processor (DSP) 34 in the receiver processing block 18. One of the functions of the DSP is to generate automatic gain control (AGC) signals that control the gain stage 16. Since the DSP is a digital component and the gain stage is analog, a digital to analog converter (DAC) 36 is required in control signal path 22.
The gain stage 16 in FIG. 2 is required to ensure that the signals input to each of the ADCs 32a and 32b are within the dynamic operating range of the ADC. If the received amplitude is relatively low, then a relatively large gain is applied in gain stage 16, whereas a relatively small gain is applied when the received signal amplitude is relatively high. This allows the use of lower resolution ADCs than would otherwise be required in order to operate over a full range of expected received signal strengths. Since the cost and power consumption of ADCs increases with resolution, receivers such as receiver 20 with AGC arrangements cost less and consume less power than those without AGC. For example, assuming that receiver 20 is to operate over a range of received signal strengths from xe2x88x9230 dBm to xe2x88x92120 dBm, representing a dynamic range of 90 dB, then in the absence of gain stage 16, the required input dynamic range of the ADCs 32a and 32b would also be 90 dB. In order to operate over this range, a 15-bit ADC would be required. With AGC however, the gain control algorithm used by the DSP 32 can be designed to accommodate virtually any desired ADC dynamic range.
FIG. 3(a) shows a plot of a typical carrier signal in the complex IQ plane. As known to those skilled in the art, such a signal would appear in IQ space as a point following a circular path with radius A, proportional to signal amplitude, at a rotation rate proportional to frequency f. Ideally, the gain stage 16 operates on a signal with amplitude A to apply gain k and thereby generate a signal with amplitude kA. As shown in FIG. 3(a), the original and amplified signals are centred on the origin of the IQ plane. Unfortunately, ideal operating conditions are seldom achieved. Even a pure carrier signal would normally not be exactly centred at the IQ origin in a real system.
In integrated receivers, most of the components shown in FIG. 2 are realized on a single printed circuit board (PCB). This can result in feeding back of signals from circuit components through the PCB to other components. In receiver 20 the fref input to the quadrature mixer 26 can be xe2x80x9cpicked upxe2x80x9d at the input of gain stage 16, causing a DC offset or shift in the centre of the IQ complex signal away from the origin. As the DC offset increases, more error is introduced in the I and Q components, increasing the receiver symbol error rate. Since the I and Q components causing the DC offset are picked up at the gain stage input, the offset increases for higher gains. This effect is shown in FIG. 3(b). For increasing gains k1, k2 and k3, the DC offsets (I1, Q1), (I2, Q2) and (I3, Q3) also increase.
According to a known technique, DC offset in a received signal can be estimated using an averaging filter. The filter is a discrete approximation of an exponential filter and has a transfer function of (1-c)/(1-czxe2x88x921). For the estimate to be insensitive to variations in the CBB spectrum, c is chosen such that the time constant is several times less than the smallest spectral component. A major disadvantage of this known technique for radio modems is that the filter has a long time constant relative to the symbol rate (usually several thousand symbols) and therefore responds slowly when the DC offset changes due to AGC changes as shown in FIG. 3(b). Every time a new gain is applied in gain stage 16, typically several thousand symbols are received before the DC offset estimate from the averaging filter is accurate.
In mobile communication environments, particularly in fading conditions wherein received signal levels fluctuate rapidly and thus the gains applied in gain stage 16 must be changed relatively often, receiver performance degrades severely because the DC estimation filter cannot quickly track the DC offset changes due to AGC changes. Some mobile communications systems also use intermittently keyed base stations, which further exacerbates the DC offset estimation problem. In such systems, a received signal can quickly change from very low amplitude noise signal, to which high gain will be applied in gain stage 16, to a high amplitude signal, to which a low gain will be applied. This switching between very different gains and very different resultant DC offsets results in increased errors when the gain is changed, such that sensitivity for detection of such intermittently keyed base stations is drastically reduced.
A wireless communications receiver is provided that comprises means for applying a gain to a received signal, responsive to an AGC signal, to produce a scaled signal; AGC means for determining amplitude of the scaled signal and generating the AGC signal; and means for estimating a DC offset of the scaled signal, wherein the means for estimating the DC offset reads a previously estimated and stored DC offset value from a memory means.
A gain control and DC offset estimation method according to one embodiment of the invention comprises the steps of applying a gain to a received signal, responsive to an AGC signal, to produce a scaled signal; determining amplitude of the scaled signal; generating the AGC signal based on the amplitude of the scaled signal and an AGC algorithm; estimating a DC offset of the scaled signal to generate an estimate; and updating a storage location in a memory means with the estimate, wherein the step of estimating the DC offset comprises a step of reading a previously stored estimate from the memory means.
Embodiments of the invention may also be embodied in a software program stored on a computer-readable medium, which when executed by a processor in a receiver performs the method steps of providing an AGC signal to a gain stage in the receiver to control a gain applied to the received signal, the gain stage producing a scaled signal; determining an amplitude of the scaled signal; generating the AGC signal based on the amplitude of the scaled signal and an AGC algorithm; estimating a DC offset of the scaled signal to generate an estimate; and updating a storage location in a memory means with the estimate, wherein the step of estimating the DC offset comprises a step of reading from the memory means a previously stored estimate corresponding to the value of the AGC signal.
Another aspect of the invention provides a wireless communications receiver comprising an antenna for receiving a communication signal, a receiver front end comprising means for filtering, amplifying and down-converting the communication signal received by the antenna, means for applying a gain to the signal output by the receiver front end to produce a scaled signal, the particular applied gain being controlled by an AGC signal, in-phase (I) and quadrature (Q) signal component processing means for separating the I and Q components of the scaled signal, and ADC means for converting the separated I and Q components to digital signals, the invention may be implemented in a DSP comprising AGC means for determining amplitude of the I and Q components and generating the AGC signal, and means for estimating a DC offset of the I and Q components to generate a DC offset estimate, wherein the means for estimating the DC offset reads a previously stored DC offset estimate from a memory means.
The AGC signal has a finite number of possible values, and the memory means stores a previously estimated DC offset corresponding to each possible value of the AGC signal. In one embodiment, the memory stores a unique estimate corresponding to each possible value of the AGC signal, whereas in an alternate embodiment, the number of DC offset estimates stored in the memory means is less than the finite number of possible values of the AGC signal, such that at least one of the stored DC offset estimates corresponds to more than one of the values of the AGC signal.
The disclosed AGC scheme operates to maintain a scaled signal output from a controlled gain stage within a desired dynamic range when a received signal is within the dynamic range of the receiver. The invention also preferably removes DC offset from the scaled signal using the estimated DC offset.
Implementation of the invention in hardware, software or a combination of both, such as in a DSP, is contemplated.
The present invention is preferably configured to operate in conjunction with wireless modems, wireless hand-held communication devices, personal digital assistants (PDAs), cellular phones, two-way pagers and other wireless communication devices and systems, as well as many other types of systems.
Further features of the invention will be described or will become apparent in the course of the following detailed description.